Session30 Compute-in-Memory.pdf

1、ISSCC 2026SESSION 30 Compute-in-Memory30.1:A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes 2026 IEEE International Solid-State Circuits Conference1 of 50A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W M

2、XFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Widthand Serial-Dual-Bit-Sliding SchemesXing Wang1,2,Yucheng Du1,Tianhui Jiao1,Defa Wu1,Xi Chen1,Miaoyu Tang1,Yi Yang1,Zhichao Liu1,An Guo1,Gaoming Fu3,Peng Li3,Jun Dong3,Bo Liu1,XinningLiu1,Weiwei Shan1,Hao Cai1,Guangyu Sun4,Lin Tong3,Jun Yan

3、g1,2,Xin Si11Southeast University,Nanjing,China2National Center of Technology Innovation for EDA,Nanjing,China3Xiaomi,Beijing,China4Peking University,Beijing,China30.1:A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-S

4、liding Schemes 2026 IEEE International Solid-State Circuits Conference2 of 50Outline Motivations,challenges and solutions Proposed MXFP-CIM with adaptive PBWConfiguration and overall structureDual-bit sliding FP-MACTwin-stage allocation schemeMapping scheme and hidden-bit decoder Simulation,measurem

5、ent and demonstration Conclusion30.1:A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes 2026 IEEE International Solid-State Circuits Conference3 of 50Outline Motivations,challenges and solutions Proposed

6、MXFP-CIM with adaptive PBWConfiguration and overall structureDual-bit sliding FP-MACTwin-stage allocation schemeMapping scheme and hidden-bit decoder Simulation,measurement and demonstration Conclusion30.1:A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Pre