Session37 Memory Interface.pdf

1、ISSCC 2026SESSION 37 Memory Interface37.1:A 72Gb/s/pin Single-Ended Driver-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets and Memory Interfaces 2026 IEEE International Solid-State Circuits Conference1 of 36A 72Gb/s/pin Single-Ended Driver

2、-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peakingfor Chiplets and Memory InterfacesHongzhi Wu,Xuxu Cheng,Yangyi Zhang,Xiongshi Luo,Zhenghao Li,Weitao Wu,Quan PanSouthern University of Science and Technology,Shenzhen,China37.1:A 72Gb/s/pin Single-Ended D

3、river-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets and Memory Interfaces 2026 IEEE International Solid-State Circuits Conference2 of 36Outline Motivation TRX Architecture and InnovationsTRX ArchitectureDriver-Cooperative Coded PAM3 Codi

4、ng SchemeTX-Side Asymmetric EQ&Bias-Peaking TechniqueRX-Side Impedance Tuning&Calibration TechniqueForwarded Clock Schemes Measurement Results Conclusion37.1:A 72Gb/s/pin Single-Ended Driver-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets

5、and Memory Interfaces 2026 IEEE International Solid-State Circuits Conference3 of 36Outline Motivation TRX Architecture and InnovationsTRX ArchitectureDriver-Cooperative Coded PAM3 Coding SchemeTX-Side Asymmetric EQ&Bias-Peaking TechniqueRX-Side Impedance Tuning&Calibration TechniqueForwarded Clock

6、Schemes Measurement Results Conclusion37.1:A 72Gb/s/pin Single-Ended Driver-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets and Memory Interfaces 2026 IEEE International Solid-State Circuits Conference4 of 36Motivation:D2D&MEM Trends D2D a