DCON26_PAPER_Track09_AdaptiveSerDesPowerScalingforSystemEnergyEfficiencyOptimization_63_45.pdf

1、 Adaptive SerDes Power Scaling for System Energy Efficiency Optimization Davide Tonietto,Huawei Technologies Canada Peter Krotnev,Huawei Technologies Canada Abstract Explosive computing growth fueled by the AI revolution is putting enormous pressure on energy efficiency and as number of cores and co

2、nnection bandwidth increases exponentially,serial links are becoming the#1 energy expenditure.It is estimated that serial links consume between 30%and 60%of the total computing&switching power.Besides being an overall energy consumption problem,this brings a variety of architectural challenges,such

3、as the power delivery and heat dissipation management.One of the reasons contributing to the rapid increase of serial link power consumption is the inability of most SerDes to adapt significantly their power consumption to the requirements of the channel they operate on.Most GPU or ASIC are built wi

4、th only one type of long reach(LR)SerDes on die but in a real system they will operate on a vast variety of backplane,chip to chip or chip to module links that vary enormously in complexity from XSR(Extra Short Reach)to VSR(Very Short Reach)to LR.However,most SerDes can only marginally adjust their

5、consumption and this is achieved by a static,manual and error prone process.Therefore,most links use more energy than necessary.In this paper we present a fully automatic power management that can dynamically reduce a DSP based LR SerDes consumption in excess of 50%depending on channel requirements.

6、This is achieved on the fly,mission mode,while the link margin is kept constant independently from channel conditions.The principles,the architecture and the design of the management system along with the optimization parameters used to operate efficiently are reviewed.Test results from a power scal