DCON26_PAPER_Track12_AI-DrivenEmulationofPowerSupplyRippleviaHSSJitterAnalysisTIE-BasedSourceIsolationforPI_263_75.pdf

1、 AI-Driven Emulation of Power Supply Ripple via HSS Jitter Analysis and TIE-Based Source Isolation for PI-SI Co-Design Niranjan Hegde,Tektronix Shubha B,Tektronix Srikrishna N.H.,Tektronix Abstract As high-speed digital systems advance into the gigahertz range,ensuring power and signal integrity bec

2、omes more difficult due to lower supply voltages and rapid switching.Power supply ripple can cause jitter,negatively affecting bit error rates.This paper presents a machine learning-based software method that analyzes Time Interval Error(TIE)spectra to emulate and isolate power supply induced jitter

3、(PSIJ).By mapping noise signatures,the technique enables engineers to link power rail fluctuations to signal quality,identify key jitter sources,and optimize decoupling early,minimizing costly design revisions and improving system robustness.Authors Biography Niranjan Hegde,Power Software Engineer w

4、orking with Tektronix,holds an M.Tech from BITS Pilani and a B.E.from RVCE.His professional expertise spans embedded systems,motor analysis,and wide bandgap(WBG)semiconductor analysis,with a strong focus on research-driven development in power electronics and system design.Shubha B is a Senior Produ

5、ct Manager at Tektronix with a background in electronics engineering and an MBA in marketing.She specializes in product strategies for semiconductor validation and workflows for WBG devices.With experience in both technical and market-facing roles,she brings a unique perspective to power electronics

6、 innovation.Srikrishna NH holds a BE from Bangalore University and an MS in Telecommunication and Software Engineering from Illinois Institute of Technology,Chicago.He has 22+years of industry experience and working with Tektronix as a Principal engineer focused on Power portfolio solutions.He has c