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DC25_PAPER_TRACK01_ChipOnBoardAndModified_Khan.pdf

2026-05-16
文档编号:1240713
文档页数:16
文档大小:1.37MB
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1、 Information Classification:General Chip-On-Board&Modified-SAP Design for the 100G PAM4&Beyond Active Cable&Optical Transceivers Rehan Khan,Infraeo Inc.Xianlong Zeng,Shenzhen Wandtec Optronics Co.Ltd.Yu Lei,Shenzhen Wandtec Optronics Co.Ltd.Tianyu Zhao,Infraeo Inc.Neema Shafigh,Alphawave Semi Inform

2、ation Classification:General Abstract This paper introduces the first industry production cable build using bare die retimer,anticipated in Q4 2024,which marks an advancement in 800G cable technology.By eliminating the package and interposer,our design achieves superior signal integrity performance,

3、through pin map,packaging,layout,etc.The simulation results based on our current 112G designs prove the achievement,comparing Known Good Die(KGD)configurations with traditional packaged configurations.The new design also offers enhanced thermal performance,as Thermal Interface Material(TIM)and heats

4、inks can be applied directly to the die,mitigating thermal dissipation issues associated with packages.Moreover,this technology is 224G ready and versatile,applicable to both optical and active copper solutions.The paper aims to share valuable engineering practices and 224G design insights,highlight

5、ing both the innovations and the challenges encountered in this state-of-the-art technology.Author(s)Biography Rehan Khan owns B.S and M.S degrees in Electrical Engineering.He has over 25-year experience in high-speed interconnect product design and development,including 400G/800G/1.6T I/O DAC/ACC/A

6、EC,high-speed connectors,optical transceivers and AOCs.Currently he is the Vice President of Applications Engineering at Infraeo.Xianlong Zeng received his B.S in Electrical Engineering from Hunan University.He has over 10-year experiences in analog and digital circuit development and high-speed har

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