DC25_PAPER_Track09_PostFECBERAnalysisof200Gbs_Barrie_V2.pdf

1、 Post-FEC BER Analysis of 200 Gb/s Wireline Systems using an FPGA Platform Richard Barrie,University of Toronto richard.barrieisl.utoronto.ca Ming Yang,University of Toronto/Alphawave Semi ming.yangisl.utoronto.ca Hossein Shakiba,Huawei Technologies Canada Anthony Chan Carusone,University of Toronto

2、/Alphawave Semi tony.chan.carusoneisl.utoronto.ca Abstract As wireline communication links transition from 100 Gb/s to 200 Gb/s per lane,new and complex forward error correction(FEC)architectures have been adopted to achieve low bit error ratios(BERs).It is essential to understand how these architec

3、tures impact link performance under various channel conditions.However,software-based time-domain simulations are incapable of demonstrating sufficiently low post-FEC BERs in a reasonable amount of time,and existing statistical BER analysis techniques are incapable of accurately modeling the complex

4、 FEC architecture proposed for 200 Gb/s wireline systems.This paper presents a flexible platform for field-programmable gate array(FPGA)-accelerated time-domain BER simulations.The platform includes functionality to model wireline systems relevant to the upcoming 200 Gb/s Ethernet standard that incl

5、ude multi-part links,concatenated FEC,soft-decision(SD)decoding,and convolutional interleaving.This FPGA platform can accurately demonstrate post-FEC BERs at the 10-12 level within a day of simulation time,a speed improvement by a factor of at least 10,000 over software-based simulation platforms.Au

6、thors Biography Richard Barrie received his M.A.Sc.degree from the University of Toronto in 2024.His research interests are in system modeling and design for high-speed communications.Ming Yang received his Ph.D.from the University of Toronto in 2024.He works as a systems engineer at Alphawave Semi.