DC25_PAPER_Track05_InnovativeInterposerSolutionsforHBM_Ilamparidhi_V6.pdf

1、 Information Classification:General Innovative Interposer Solutions for HBM3/4:A Path to 12.8Gbps Ilamparidhi I,Alphawave Semi Suriya Prakash T,Alphawave Semi Gangaraju M,Alphawave Semi Yadavalli Jagadeeswari,Alphawave Semi Diksha Acharya,Alphawave Semi Diksha.A Information Classification:General Ab

2、stract The AI boom is driving the memory industry towards HBM4 at 12.8Gbps,doubling Interface Width from 1024 to 2048.Semiconductor foundries are enhancing 2.5D and 3D packaging solutions for seamless HBM3&HBM4 to SoC integration,addressing layout and SI-PI challenges due to increased crosstalk and

3、loss from higher I/O counts and deeper micro bump pins.Achieving 12.8Gbps HBM3/4-to-SoC integration requires systematic optimization of layout and SI-PI aspects.This paper demonstrates an efficient SI-PI layout optimization methodology,developed alongside a novel crosstalk shielding structure 110 th

4、at significantly reduces crosstalk,enables higher speeds for HBM3 and HBM4.Our methodology is novel because it:1.Leverages 2D and 3D-EM tools to balance accuracy and extraction time.2.Characterizes the interposer with Voltage Transfer Function(VTF)based Insertion-Loss(IL),Power-Sum-Crosstalk(PSXT),a

5、nd Insertion-Loss-to-Crosstalk Ratio(ICR).3.Decomposes interposer-induced jitter into ISI,crosstalk,and rise-fall time degradation to identify the dominant channel parameter affecting EYE closure,facilitating better layout and I/O architecture optimization.This paper addresses critical industry ques

6、tions for achieving 12.8Gbps by evaluating Silicon(Si)&Organic(RDL)Interposers,determining optimal variants,stack-up layers,and routing pattern for HBM3/4-12.8Gbps.We provide a system-level jitter budget indicating available margin at 12.8Gbps and assess the need for I/O architecture enhancements su