DC25_PAPER_Track2_ModelingAndStudyOfNonLinearity _Bhardwaj_Final.pdf

1、 Information Classification:General Modeling and Study of Non-Linearity in double data date(DDR)Memory Links Kanupriya Bhardwaj,AMD ,650-714-9791 Information Classification:General Abstract The demand for high-speed memory in server applications entails multiple parallel lanes running at high data r

2、ates,leading to crosstalk dominated channels.While the focus has been towards signal integrity(SI)related optimization,accurate estimation and modeling of other dominant channel impairments is also essential for a robust design.Due to the single-ended nature of the signal and the large swings,receiv

3、er non-linearity in DDR links cannot be ignored.In this paper,we discuss the implications of receiver non-linearity on link performance in DDR space.We also present results based on a methodology for the modeling of receiver analog front-end(AFE)non-linearity.Furthermore,two indirect methods are pre

4、sented to model and account for the impact of non-linearity on link margins for use in linear time invariant(LTI)-based statistical analysis tools.Author(s)Biography Kanupriya Bhardwaj received the B.Tech.and M.Tech.degrees in Electrical Engineering from IIT Kharagpur,India,in 2007,and Ph.D.from Sta

5、nford University in 2013.She has since worked at Intel and Altera and is currently at AMD,working on performance modeling of links.Information Classification:General Introduction As we move towards higher data rates and multiple,area-optimized,parallel lanes in DDR structure on system-on-a-chip(SoCs

6、)to support high throughput,the margins in DDR links keep on shrinking.These dense lanes are dominated by crosstalk.To achieve an area and power efficient design of a DDR Host,it is important to model all design non-idealities in a realistic manner so that their impact can be budgeted appropriately.