DC25_PAPER_TRACK1_StatisticalModelingOfSystemPowerIntegrity_Sharma.pdf

1、 1 Public Design Con 2025 Statistical Modeling of System Power Integrity in Adaptive Embedded SoC for Artificial Intelligence(AI)Computing Ajay Kumar Sharma,AMD Inc.Susmita Mutsuddy,AMD Inc.Adiu Chen,AMD Inc.Ge Chang,AMD Inc.Hing“Thomas”To,AMD Inc.2 Public Abstract AI computing has proliferated acro

2、ss numerous System-On-Chip(SoC)platforms,from cloud computing environments in data centers to edge AI platforms like AI vision in the Industrial Internet of Things.Ensuring power integrity is essential for optimal performance in any computing system.Unlike traditional platforms,AI computing platform

3、s are highly diverse.Designing an optimal Power Delivery Network(PDN)for such varied systems is challenging due to differences in physical platforms and use cases.While many previous publications have detailed the design of PDN,this paper introduces a statistical framework to evaluate use-case curre

4、nt profiles.Voltage noise,which is the Figure of Merit of consideration,is the product of current profile and power delivery network impedance.This framework allows optimization of voltage noise performance in conjunction with system PDN design.By applying the probability of enabling individual comp

5、ute element arrays to activity-based current profiles,the framework generates effective current excitations according to the use-cases.Additionally,the framework incorporates the statistical distribution of triggering times among computing elements.This statistical probability is based on user knowl

6、edge.An AI SoC system was tested using application-based scenarios.This analytical framework was validated through direct voltage noise probing and on-die voltage monitor measurements.The framework generates realistic effective current excitations(di/dt)for the system PDN design,identifying and quan