DC25_SLIDES_TRACK02_ModelingGDDR7PAM3DualBranch_Allred.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralModeling GDDR7 PAM3 Dual Branch Receiver with IBIS-AMIRichard Allred,(The MathWorks)Eric Brock(The MathWorks),Tripp Worrell(The MathWorks),Esa

2、 Adil(The MathWorks)2Information Classification:GeneralImageSPEAKERSRichard AllredPrincipal Software Engineer,The MathW|Principal software engineer at The MathWorks with 17 years of signal integrity experience with Intel,Inphi,and SiSoft.He received his Ph.D.from the University of Utah in 2021.3Info

3、rmation Classification:General GDDR7 JEDEC RAM specs released in March 2024 32 Gbps(per pin)Dual branch architecture PAM3Introduction to GDDR74Information Classification:General When both branch decisions agree:output PAM3 symbol is 0 or 2.When branch decisions disagree:output PAM3 symbol 1.5PAM3 to

4、 Branched NRZ and back to PAM32 0 0 0 0 2 0 2 1 1 1 1 1 1 1 2 2 2 2 1 0 2 0 0 0 0 2 0 2 1 1 1 1 1 1 1 2 2 2 2 1 0 Upper Brach DecisionLower Branch DecisionOutput PAM3 Symbol00001110NA112Information Classification:General What information,or insight,do we have about the circuit?o LTI or non-LTI?o AC

5、sweeps available?o Multiple stages?o Expected dynamic input range?Peaking Filter Modeling Overview6Information Classification:GeneralSingle Stage Peaking Filter Modeling Options7Information Classification:General Small signal stimulus:50 mVpp PRBS waveformBlack Box Modeling of Single Stage CTLE(1/5)

6、8Information Classification:General What is a memoryless non-linearity(MNL)?Monotonic For differential,symmetric about 0 V Typically modeled as a lookup table of voltage in versus voltage outBlack Box Modeling of Single Stage CTLE(2/5)9Information Classification:General Large signal stimulus:600 mVp