DC25_SLIDES_Track12_TutorialChannelDeEmbeddingMethodology_Choi_V2.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralChannel Embedding/De-Embedding Methodology for Rx Stress Testing Using Fast-Edge Tx Waveform of BERTYoonman Choi,SK hynixKwang-rok Kim,Keysight

2、2Information Classification:GeneralImageImage SPEAKERSYoonman ChoiSenior App Engineer,SK hynixY|Senior application engineer of MPHY/PCIe/SATA for storage device solutions.Located in Seongnam-Si,Gyenggi-do,Korea.Kwangrok KimApplication engineer,KeysightKwang-|Kwang-Rok Kim is an Advanced Solution eng

3、ineer at Keysight Technologies.He received his Bachelors degree in electronic engineering.He joined Keysight Digital team in 2019 and works on High speed digital application and Solution Engineering in Digital.Prior to 2019 he worked in the areas of system integration,programming development,automat

4、ion.3Information Classification:GeneralIntroduction4Information Classification:GeneralProblem Statement5 Most commercially available standardized high-speed serial IOs define the receiver compliance or conformance tests using the worst case channel scenario which have the maximum channel loss.To eva

5、luate the overall receiver performance with the worst case channel,the Bit Error Rate Tester(BERT)is a commonly used for receiver compliance or conformance tests as a test signal source.But,even when the DUT can tolerate the DC/AC input voltage tolerance(ITOL)or receiver jitter tolerance(JTOL)with t

6、he worst case channel,if we replace the test signal source from BERT to real silicon,we find a margin issue or complete fail results.If we replace the signal source from BERT Tx to the actual host/device silicon Tx,is it possible to guarantee the channel Rx margin with the same test channel?Or if we