DC25_SLIDES_Chiphead_PanelTheExpandedRoleOf_Loberg.pdf

1、Welcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Panel The Expanded Role of SI/PI in GenAI Data Center DevelopmentChris Loberg-TektronixSteve Sandler-PicotestLouie Lu Meta InfrastructureDr.Teng Long Cambridge UniversityJosiah Bartlett-TektronixIndustry Overvi

2、ewChallengesPanelists PerspectivesDiscussion/Q&AAgendaThe Impact of GenAI on Data Center EfficiencyChallenges for Data Center Design TeamsIt is a new frontier-No one knows the right questions to ask about design validationHigh current leads to more questions around proper Power Distribution Network(

3、PDN)topology.New components(e.g.,a 30 PDN)present new characterization challenges.How to measure this?How tomeasurelarge signal and small signal stabilityof PMICs andCorePower dissipation is much higher.Need to measure/account/model out the loss.Future architecture needs.How to prepare for 2000 amp+

4、GPU technology.How to measurepower rail noise?6System Design ComponentsProcessors,GPUs,SoCs,FPGAsSerDes High-speed dataLots of power rails with dynamic voltage managementEfficiency and heat managementPoint of load power regulation and digital power managementPower Integrity affected by noiseNoise so

5、urces on power rails(higher frequencies)Dynamic core currentCross talk from data signals,Coupling from clocks,Power supply switching noise(and harmonics)What happens if power rails are noisy?Jitter bit errors,other reasonsDriving power rail specifications that require high accuracy ripple measuremen

6、tsAreas of Impact7Trends in GenAI HW DesignTrendCauseDesign challengesMitigationSoC IO explosionHigh scale-up communication BWSI:longer end-end channel,higher data rateLayout:more Serdes to escape&routeFlyover cable,retime,CPOSoC Power explosionHigh power compute chipletdI/dt:larger transient,bot ca