DC25_SLIDES_TR13_ViaDesignFor112GbpsAndBeyond_Manukovsky 2025-01-24 15.07.46.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralVia Design for 112 Gbps and Beyond:Theory and RealityAlex Manukovsky,IntelYuriy Shlepnev,Simberian Inc.Joshua Nutzati,IntelAlexander Kuntsevych

2、,IntelItzhak Peleg,Intel Shimon Mordooch,Intel 2Date:Thursday,January 30 8:00 AM-8:45 AM Pacific TimeLocation:Ballroom BInformation Classification:GeneralIntroductionBandwidth and LocalizationDesign of Vias for Two StackupsReality CheckNew Approach to Viahole Design ConclusionOUTLINE3Information Cla

3、ssification:General Designing PCB and packaging interconnects for 112-224 Gbps linkspresents multiple challenges Design of vertical transitions,or vias,being one of the most criticalelements and is the main roadblock for 448 Gbps links Vias dissipate and reflect signals,contribute to crosstalk noise

4、 through both local and distant coupling How to approach the via analysis and design at these data rates?.Introduction4Information Classification:GeneralState of the Art in Via Analysis5 3D EM for RL,IL and Local Coupling of Viaso FEM HFSS;FEM+DD Clarity;BEM-HyperLynx 3D EM;FIT CST;Simbeor MoL,TFE;2

5、D EM for Long-Distance Coupling of Viaso Physics-based local via model+transmission plane model for PDNo Power SI,SI Wave,HyperLynx SI+PIo Possible accuracy improvement for some geometries with near-field and far-field separation(validated up to 100 GHz)Hybrid 2D+3D EM Local and Long-Distance Coupli

6、ngo PEEC,FEM,DGTD,o Still at research stageSee references and details in the paperInformation Classification:GeneralVia Design Approaches6S.McMorrow,Breakout Design:Packageand Traces,Samtec,gEEk spEEk,2023 zones of controlA.Carmona-Cruz,K.Scharff,J.Cedeo-Chaves,H.-D.Brns,R.Rimolo-Donadio and C.Schus