DC25_Slides_Track04_StudyofTDRimpedanceand_Tang_V2.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralStudy of TDR impedance and loss based on modified Cannonball-huray roughness model on a 1.6Tbps optical module PCBSpeaker:Yinfei Weng,(Xpeedic)

2、Rongyao Tang(Fiberhome),Shengyao Wan(Fiberhome)Rui Wang(Xpeedic),Zhi Li(Shennan Circuits)2Information Classification:GeneralSPEAKERSYinfei WengAE Manager,X| Yinfei Weng is currently the AE Manager at Xpeedic Co.,Ltd.He has over 10 years of experience in high-speed systems and advanced packaging.His

3、research interests focus on signal integrity,power integrity,and computational electromagnetics.3Information Classification:General4ZTE,2023Evolution Process of DAC/ADC Signal Baud RateInformation Classification:General5Capacity of Ethernet Switching ChipsInformation Classification:GeneralOE Channel

4、s(DAC/ADC):oBaud rate improved from 32 GBd to 120 GBd.o3 dB bandwidth increased from 18.4 GHz to over 70 GHz,a fourfold increase.High-Speed SerDes Channels:oBit rate per lane increased from 10 G to over 200 G.oNyquist frequency increased from 5 GHz to over 50 GHz,a tenfold increase.PCB loss simulati

5、on in the DC to 70-90 G ultra-wide frequency band is importantHSD&RF Signal in Coherent Optical Module6Block diagram of optical moduleInformation Classification:GeneralManufacturing Processes for Coherent Optical Module PCBs7PCB Material：20GHz Df0.002，CTE X/Y-Axis 10 ppm/Copper Foil：Ultra Low Profil

6、e(HVLP)，matte side Rz2umHDI Processo12-16 layers stackup&N+2+N Buildupolaser-drilled blind vias&any-layer interconnectsoFine linesmSAP Process：ultra-fine lines&60um viaInformation Classification:GeneralTechnological Advancement for Coherent Optical Module PCBs8Information Classification:GeneralmSAP