DC25_SLIDES_Track8_NavigatingTheIntricaciesOfPcieGen6_zahrein.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralNavigating the Intricacies of Pcie Gen6 Electrical PerformanceBin Yaacob,Zahrein(Altera)2Kong Chooi Yee(Altera),Chng,Claris Jing Wen(Altera),H

2、oang,Thanh(Altera),Kho Boon Hock Joseph(Altera)Information Classification:GeneralImageSPEAKERSBin Yaacob,ZahreinEV Engineer,AZahrein Yaacob is a seasoned electrical validation engineer at Altera with 20 years of experience,specializing in high-speed I/O validation across protocols such as OIF-CEI,IE

3、EE,HDMI,DisplayPort,PCI-SIG,and USB.He currently leads PAM4 electrical testing,driving the transition from 53 Gbps to 224 Gbps,while addressing the challenges of next-generation high-speed data transmission to ensure interface integrity and optimal performance.3Information Classification:General Int

4、roduction PCIe Gen 6 electrical validations PCIe Gen6 TX Test PCIe Gen6 RX Test PCIe Gen6 Test cases SummaryOutline4Information Classification:GeneralPCIe Gen 6 Electrical Testing What is PCIe Gen 6?PAM4 signalling Data rate is at 64 Gbps New Test parameters due to PAM4 Require upgrade on Test Equip

5、ments Different Spec Test parameters on TXAnd RX.What is done to qualify the IP?Intrinsic validations and meeting the Base Spec.5Information Classification:GeneralPCIe Gen 6 TX Electrical testing TX parameters are measured at the DUT.De-embedding the channel is required at the Scope.Real Time scope

6、is used to accommodate accurate measurement with SSC refclk.Measured with SSC(spread spectrum clock),and SRIS(Separate reference independent spread).6Information Classification:GeneralBench Setup7Hardware Test SetupSilicon labs refclk GeneratorRefclk:100 MHzSSC and SRIS.Infinium Scope UXR UXR1002A 1