DC25_SLIDES_Track1_StatisticalModelingOfSystemPowerIntegrity_Sharma_V2.pdf

1、Information Classification:GeneralPublicWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralPublicStatistical Modeling of System Power Integrity in Adaptive Embedded SoC for Artificial Intelligence(AI)Computing Ajay Kumar Sharma

2、,(AMD)Thomas To,(AMD)Ajay Kumar Sharma(AMD),Thomas To(AMD)Susmita Mutsuddy(AMD)2Information Classification:GeneralPublicImageImage SPEAKERSAjay Kumar SharmaPMTS,AMDAjay.Kumar.Sis a Principal Engineer at AMD.He is involved in Signal integrity characterization including SSN,PDN&Memory system character

3、ization.He joined Xilinx in July 2011.Ajay completed his M.Tech.from Thapar Institute of Engineering&Technology in 2005.Before joining Xilinx,Ajay was leading a Signal Integrity&Package Design team at Freescale Semiconductor India Pvt.Ltd.Thomas ToSenior Fellow,AMDThomas.T,AMDis a Senior Fellow in A

4、MD focusing on System IO Platform Architecture Development.Prior to AMDs acquisition of Xilinx,Thomas was a Distinguished Engineer in System Memory Signal Integrity group.Before joining Xilinx,Thomas was with NVIDIA Advanced Technology Group focused on highspeed circuits&system channel designs.Befor

5、e NVIDIA,Thomas worked for Intel for more than 16 years covered and led many different types of system memory IO development.Thomas received his PhD degree in Electrical Engineering from the Ohio State University&he is the inventor of over 40 patents in the fields of mixed signal IO circuits and sys

6、tem memory configurations as well as high speed clocking for highspeed memory designs.3Information Classification:GeneralPublic Overview of Embedded SoC for AI Computing Growth Trend and Challenges for Power Integrity Design Overview of Adaptive Embedded SoC Statistical Power Noise Analysis Set Up S