DC25_SLIDES_Track02_EffectiveContinuousTimeLinearEqualizer_LIU.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralEffective Continuous Time Linear Equalizer Modeling using Dual-Transfer FunctionsPeter Krotnev(Huawei Canada)Siqi Liu(Huawei Technologies),Tian

2、yu Liang(Huawei Technologies),Xusheng Liu(Huawei Technologies),Honggang Tang(Huawei Technologies),Wenquan Yang(Huawei Technologies)2Information Classification:GeneralImageSPEAKERS3Peter KrotnevSenior Principle Engineer,Huawei CanadaPA Sr.Principal Engineer at Huawei Technologies,signal integrity exp

3、ert and a member of the High Speed I/O System Development Team.Peter is responsible for SerDes architecture improvements,electrical specifications,test planning,measurements,as well as leading the development of the SerDes tuning and optimization strategies for power and performance.Information Clas

4、sification:General1.Challenges in High-Speed I/O Interface Modeling2.CTLE Modeling in Statistical Domain3.Dual-Transfer Function Modeling Method4.Experimental Results5.SummaryTopics4Information Classification:General1.Challenges in High-Speed I/O Interface Modeling2.CTLE Modeling in Statistical Doma

5、in3.Dual-Transfer Function Modeling Method4.Experimental Results5.SummaryTopics5Information Classification:GeneralSI Performance Degradation with I/O Data rate Growing6Standard MemoryExample：Memory and Buffer Interface Demands Growing Expectation.IL&RL degradation with I/O speed.The data rate increa

6、se of I/O interface brings challenges to SI design.Information Classification:GeneralSI Electrical Model of High-Speed I/O 7SoC PHY PLL/CLK Common Path/CLK Local Path/P2S Jitter IO TX Pre-Driver/Post Driver Jitter&Noise IO RX CIO/CTLE/DFE VDDQ&VDD Power Supply NoiseChannel T-Coil SoC Package Mother