DC25_SLIDES_Track1_ReducingChipsRespinRate_Zamek.pdf

1、Information Classification:GeneralWelcome to Reducing Chips Respin Rate by Fixing Common Decoupling Methods Flaws1ILIYA ZAMEKInformation Classification:GeneralSemiconductor industry losses on chips re-tape outsThe rate of chip re-tape out is increasing The growing complexity of semiconductor devices

2、,especially high-consumption HPC,GPU,and AI/ML processors lead to an increased rate of chips re-tape out(respin),according to the Wilson Research&Siemenssurvey 1.TSMC,with its 61%market share manufactured 11895 various products in 2023 2,3.Therefore,11895/0.61=19500 products were manufactured in 202

3、3 worldwide.The total number of additional respins made in the global semiconductor industry in 2023 is 19500*1.35=26,325 respins.The cost of a single chip respin as nods topology shrinks,is also increasing due to:-the increasing mask cost 4,5;-the increased expenses on design validation and verific

4、ation,which can exceed high mask costs.For example,the recent AI/ML processor development project has over 300 people and over$2 billion invested 6-8.Assuming an average cost of$3-$5 million for all necessary expenses related to a single respin.The worldwide semiconductor industry incurs losses(resp

5、in cost)*(#of respins)ranging between$80 and$130 billion yearly.The analysis of reasons for chip re-tape outs and developing methods to reduce the respin rate has become critically important.First silicon success 2020202232%24%76%of the new chips require between 2 and 7 respins in 2023 1.From data 1

6、 we estimated that a total of 2.35 tape-outs,or more than 1.35 additional re-tape outs were required per device.Information Classification:GeneralASIC Flaws leading to the chips respin The Categories of the ASIC Flaws IC flaws are shown in Fig.2,not normalized.After normalizing all categories based