DC25_SLIDES_Track9_400GElectricalPathfinding_Martin.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:General400G+Electrical PathfindingJeremy Cosson-Martin,AMDJeremy Cosson-Martin(AMD),Kevin Zheng(AMD),Shiva Kiran(AMD),Athanasios Ramkaj(AMD),Ronan Ca

2、sey(AMD),Hongtao Zhang(AMD),Jay Im(AMD),Yohan Frans(AMD),Geoff Zhang(AMD)2Information Classification:GeneralImageSPEAKERJeremy Cosson-MartinMicro Architect Design Engineer,AMDJeremy.cosson-|AMDJeremy Cosson-Martin received his Ph.D.in Electrical Engineering from the University of Toronto,ON,Canada,i

3、n 2023.His research focused on advanced high-speed wireline modulation schemes.Currently,he works as a Micro Architect Design Engineer at AMD developing next-generation high-speed wireline transceivers.He also serves on the Solid-State Circuits Society(SSCS)education committee and is the program cha

4、ir of the SSCS Arduino Contest.3Information Classification:GeneralMotivation4 Ethernet has adopted PAM4 for 50,100,200Gb/s.However,PAM4 poses considerable challenges for next-generation 400Gb/s+electrical interconnect.PAM4 Benefits:Industry adoption.Backwards compatibility.PAM4 Challenges:Achieving

5、224Gbaud with 112GHz bandwidth will consume considerable power.Channel and package Insertion Loss(IL)at 112GHz limits interconnect reach and potential applications.Information Classification:General Benefits:Reduced bandwidth requirements over PAM4.Reduced power thanks to a lower baud rate.Reduced c

6、hannel and package IL.Challenges:Backwards compatibility.FFE and CDR convergence.Requires higher Signal-to-Noise Ratio(SNR)for a given Bit-Error-Rate(BER).Increased susceptibility to external interference.Reduced tolerance to non-linearity and mismatch.Alternative#1:PAM6/8/12/165 Information Classif