SESSION 22 Memory Interface.pdf

1、ISSCC 2025SESSION 22Memory Interface22.1:A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise,Reference Offsetand Crosstalk for Chiplets and Short-Reach Memory Interfaces 2025 IEEE International Solid-State Circuits Conference1 of 36A 0.275pJ/b 42Gb/s/pin Clock-Reference

2、d PAM3 Transceiver Tolerant to Supply Noise,Reference Offset and Crosstalk for Chipletsand Short-Reach Memory Interfaces Kahyun Kim,Jung-Hun Park,Ha-Jung Park,Jia Park,Jihee Kim,Woo-Seok ChoiSeoul National University,Korea22.1:A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supp

3、ly Noise,Reference Offsetand Crosstalk for Chiplets and Short-Reach Memory Interfaces 2025 IEEE International Solid-State Circuits Conference2 of 36Outline Motivation Proposed Clock-Referenced PAM3 Transmitter Receiver Measurement Results Conclusion22.1:A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 T

4、ransceiver Tolerant to Supply Noise,Reference Offsetand Crosstalk for Chiplets and Short-Reach Memory Interfaces 2025 IEEE International Solid-State Circuits Conference3 of 36Outline Motivation Proposed Clock-Referenced PAM3 Transmitter Receiver Measurement Results Conclusion22.1:A 0.275pJ/b 42Gb/s/

5、pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise,Reference Offsetand Crosstalk for Chiplets and Short-Reach Memory Interfaces 2025 IEEE International Solid-State Circuits Conference4 of 36Motivation D2D and MEM requires high speed,and low power interface.PAM3 has been adopted to increa

6、se data rate in GDDR.01020304050607000.511.52Data rate Gb/s/pinPower efficiency pJ/bitD2D standardsD2D papersMEM papers22.1:A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise,Reference Offsetand Crosstalk for Chiplets and Short-Reach Memory Interfaces 2025 IEEE Interna