AssertLLM：通过多 LLM 从设计规范生成硬件验证断言.pdf

1、1AssertLLM:Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs Zhiyuan Yan1*,Wenji Fang2*,Mengming Li2,Min Li3,Shang Liu2,Zhiyao Xie2,Hongce Zhang11Hong Kong University of Science and Technology(Guangzhou)2Hong Kong University of Science and Technology 3Huawei Techn

2、ologies Co.,Ltd Functional Verification Check if implementation complies with specification2RTL for hardware designassert property(ready=#3:5 valid#1 finish);SystemVerilog Assertion Implementation(RTL)Hardware description language(HDL)Specification(Assertion)Ad-hoc properties Security propertiesFunc

3、tional Verification Simulation30101101010111010101010011111Test vectorSimulationSimulation results10101101010111010101010011114Hardware Formal Verification RTL complies with predefined assertions?Behavioral Model(RTL)Property(e.g.,SystemVerilog Assertions)Model Checkingreq|-#1:4 respResult a counter

4、example,or a proofAssertion for Verification System Verilog Assertion(SVA)Need understanding of System Verilog syntax Verification techniques Hardware design5 Account for Completeness Coverageassert property(ready=#3:5 valid#1 finish);SystemVerilog AssertionAutomatic Assertion Generation Dynamic min

5、ing Simulation traces+design constraint analysis No golden reference,rely on RTL designs under verification(DUT)Static analysis of specifications Predefined templates Still need a few human efforts ML-based methods Traditional natural language processing(NLP)Large language model(LLM)6Previous ML-bas

6、ed Assertion Generation LLM-based1 Human-written specification sentences(from comments)No golden reference NLP-based2 Human-extracted specification sentences Hard to generalize across distinct grammar Waveform diagrams in specification are ignored Can we directly generate assertions from SPEC?71.Kan