通过高级综合技术增强传统硬件抵御侧信道攻击的能力.pdf

1、Making Legacy Hardware Robust against Side Channel Attacks via High-Level SynthesisMd Imtiaz Rashid,and Benjamin Carrion SchaeferMdimtiaz.rashidutallas.edu,schaferbutdallas.edu30thAsia and South Pacific Design Automation ConferenceASP-DAC 2025Department of Electrical and Computer EngineeringJanuary

2、21,2025,Tokyo Introduction What,why and how?Background information High-Level Synthesis How does it work?RTL to C for HLS compiler and modernization methodology overview Side Channel Attacks(SCAs)Proposed Flow SCA-aware RTL to C compiler Security-aware HLS design space exploration Experiments Experi

3、mental Setup Experimental Results Conclusion2OutlineWhat?Legacy RTL code(Verilog or VHDL)is mostly HW security unaware Need design flows to“modernize”this legacy RTLWhy?To protect older HW assets,e.g.,from the military that can updated infrequentlyHow?Through an RTL to C compiler coupled with securi

4、ty primitives at the behavioral level3IntroductionSecurity unawarelegacy RTLunsecureLogic SynthesisPlace and RouteCorrelation AnalysisHWTraces RPower estimation Security-awareRTL2C compilerSecurity primitivesSecurity-awareCsecureHigh-Level SynthesisLogic SynthesisPlace and RouteHWTraces RRTLsecure H

5、igh-Level Synthesis Design circuits using software languages Definition:“Automatic conversion of a behavioral,untimed description into efficient hardware that implements that behavior”Benefits1.Software programmability and hardware performance2.Faster verification3.Allows to easily re-target any beh

6、avioral description to new technologies and newer design constraints(i.e.,area,power,performance)High-Level SynthesisANSI-C/C+/SystemCHigh-Level SynthesisLogic SynthesisPlace and RouteAreaLatencyPowerGDSIITechlibTarget freqSWaP-CHigh-Level Synthesis in Practice#define pragma1 array=reg#define pragma